1. Field of the Invention
The present invention relates, in general, to a field effect transistor (FET) and method for manufacturing the same.
2. Description of the Related Art
As semiconductor devices become increasingly integrated, size (i.e., channel length) of MOS transistors has become scaled. As channel length is shortened, an integration density of the semiconductor device may be improved. However, decreasing channel length may cause a short channel effect to occur, such as a drain induced barrier lowering (DIBL), a hot carrier effect and/or a punch through. In order to reduce the possibility of such a short channel effect from occurring, it may be desirable to reduce a depth of a junction region and a thickness of a gate oxide layer in proportion to a decrease or shortening of the transistor channel length.
If the depth of the junction region is reduced, a junction resistance (RS, RD) is also reduced. In case of a relatively long channel transistor, the junction resistance does not have a substantial influence on an ‘on current’ of the transistor. However, for a short channel transistor, the junction resistance has a substantial influence and a relatively large junction resistance may greatly reduce the transistor on current. Thus, it may be desirable to improve the junction resistance characteristics of a transistor such as a MOS transistor.
The junction resistance is a function of a spreading resistance occurring at a channel edge (edge of a junction region). That is, if the spreading resistance is reduced, the junction resistance can be reduced. The spreading resistance is associated with a doping profile of a junction region. If the doping profile of the junction region can be reduced abruptly at the channel edge, referred to as ‘junction abruptness”, the spreading resistance may be reduced. Thus, the more definite the junction abruptness at a boundary between a channel edge and an adjacent layer (such as a source or drain region in the transistor), the lower the spreading resistance and hence, junction resistance.
However, conventionally in MOS transistors, the junction region is formed by an impurity ion implantation and annealing process. The doping profile at the junction region thus has an undesirable slope of at least about 3 nm/decade at the side portion of the junction region. This undesirable slope formed at sides of the junction region due to the ion implantation and the annealing process represents a substantial limitation in the efforts to reduce the spreading resistance, since desirable junction abruptness at the channel edge cannot be obtained.